1. Field of the Invention
The present invention relates to a flat-panel display.
2. Description of the Related Art
Various flat-panel displays have been investigated as image displays alternative to cathode ray tubes (CRT) which are now mainstream. Such flat-panel displays are exemplified by liquid crystal displays (LCD), electroluminescence displays (ELD), and plasma display panels (PDP). In addition, the development of flat-panel displays combined with electron emission devices has been advanced. Known examples of the electron emission devices include a cold-cathode field electron emission device, a metal/insulator/metal device (also referred to as a “MIM device”), and a surface-conduction electron emission device. The flat-panel displays combined with these electron emission devices each including a cold-cathode electron source have attracted attention from the viewpoints of high resolution, bright color display, and low power consumption.
A cold-cathode field electron emission display (may be abbreviated to a “display” hereinafter) used as a flat-panel display combined with a cold-cathode field electron emission device generally includes a cathode panel having an electron emission region corresponding to each of pixels arrayed in a two-dimensional matrix, and an anode panel having a fluorescent layer which is exited by collision with electrons emitted from the electron emission region to emit light, both panels being opposed to each other with a vacuum layer provided therebetween. Generally, at least one cold-cathode field emission device (may be abbreviated to a “field emission device” hereinafter) is provided in the electron emission region. The field emission device may be a spinto type, a flat type, an edge type, a planar type, or the like.
FIG. 9 is a conceptual partial end view showing an example of a display having a spinto-type field emission device, and FIG. 11 is an exploded schematic perspective view showing portions of a cathode panel CP and an anode panel AP. The spinto-type field emission device constituting the display includes a cathode electrode 11 formed on a support 10, an insulating layer 12 formed on the support 10 and the cathode electrode 11, a gate electrode 13 formed on the insulating layer 12, apertures 14 (first apertures 14A formed in the gate electrode 13 and second apertures 14B formed in the insulating layer 12) provided in the gate electrode 13 and the insulating layer 12, and conical electron emission parts 15 formed on the cathode electrode 11 so as to be disposed at the bottoms of the respective apertures 14.
Alternatively, FIG. 10 is a conceptual partial end view showing a display including a so-called flat field emission device having substantially planar electron emission parts 15A. The field emission device includes a cathode electrode 11 formed on a support 10, an insulating layer 12 formed on the support 10 and the cathode electrode 11, a gate electrode 13 formed on the insulating layer 12, apertures 14 (apertures 14A formed in the gate electrode 13 and apertures 14B formed in the insulating layer 12) provided in the gate electrode 13 and the insulating layer 12, and electron emission parts 15A formed on the cathode electrode 11 to be disposed at the bottoms of the respective apertures 14. The electron emission parts 15A include many carbon nanotubes partially buried in a matrix.
In these displays, the cathode electrode 11 is a stripe electrode extending in a first direction (the Y direction in the drawing), and the gate electrode 13 is a stripe electrode extending in a section direction (the X direction in the drawing) different from the first direction. The cathode electrode 11 and the gate electrode 13 are formed in stripes in different directions so that the projective images of both electrodes 11 and 13 are perpendicular to each other. The overlap region between the stripe-shaped cathode electrodes 11 and gate electrodes 13 serves as an electron emission region EA corresponding to one sub-pixel. The electron emission regions EA are generally arrayed in a two-dimensional matrix in an effective region which is a central display region having a display function as a practical function of a flat-panel display, an ineffective region being disposed outside the effective region to surround in a frame form the effective region.
On the other hand, the anode panel AP has a structure in which fluorescent layers 22 are formed in a predetermined pattern on a substrate 20 and are covered with an anode electrode 24. Specifically, the fluorescence layers 22 include red light-emitting fluorescent layers 22R, green light-emitting fluorescent layers 22G, and blue light-emitting fluorescent layers 22B. Furthermore, light absorbing layers (black matrix) 23 composed of a light absorbing material such as carbon or the like are buried between the respective fluorescent layers 22, for preventing the occurrence of color blurring of a display image or optical crosstalk. In the figures, reference numeral 21 denotes a partition wall; reference numeral 40, a spacer; reference numeral 25, a spacer support part; reference numeral 26, a frame; reference numeral 17, a converging electrode; and reference numeral 16, an interlayer insulating layer. In FIGS. 10 and 11, the partition wall, the spacer, the spacer support part, and the converging electrode are omitted.
The anode electrode 24 has the function as a reflective film reflecting light emitted from the fluorescent layers 22, the function as a reflective film reflecting electrons recoiling from the fluorescent layers 22 or secondary electrons (generically called “backscattered electrons” hereinafter) emitted from the fluorescent layers 22, and an antistatic function for the fluorescent layers 22. The partition wall 21 has the function to prevent the occurrence of so-called optical crosstalk (color blurring) due to collision of the backscattered electrons with the other fluorescent layers 22.
Each sub-pixel includes the electron emission region EA on the cathode panel side, and the fluorescent layer 22 on the anode panel side opposing a group of the field emission devices. The sub-pixels of the order of hundreds of thousands to millions are arrayed in the effective region.
The anode panel AP and the cathode panel CP are arranged so that the electron emission regions EA oppose the fluorescent layers 22, bonded together through the frame 26 in a peripheral region, evacuated, and then sealed to produce a display. The space surrounded by the anode panel AP, the cathode panel CP, and the frame 26 has a high degree of vacuum (for example, 1×10−3 Pa or less).
Therefore, the display is damaged by the atmospheric pressure unless the spacers 40 composed of, for example, a ceramic material or glass are disposed between the anode panel AP and the cathode panel CP. Furthermore, an antistatic film (not shown) composed of, for example, CrOx or CrAlxOy, is formed on the side surface of each spacer 40.
FIGS. 18, 19, and 20 each schematically show the orbits of electrons or electron beams of the sub-pixels disposed near the spacers 40. In FIGS. 18, 19, and 20, the anode electrode, the light absorbing layers (black matrix), and the converging electrode are omitted. The gate electrodes 13 extend in the vertical direction (X direction) of the drawing, and the cathode electrodes 11 extend in a direction (Y direction) parallel to the drawing.
As shown in FIG. 18, electrons passing through the anode electrode (not shown) on the anode panel AP collide with the fluorescent layers 22. As shown in FIG. 19, the electrons are partially backscattered by the fluorescent layers 22, and the backscattered electrons or the like partially collide with the spacers 40.
The backscattered electrons or the like cause various problems.
That is, the backscattered electrons or the like partially collide with the spacers 40. In general, a material such as a ceramic material or glass having an excellent withstand voltage has a relatively high total secondary electron emission coefficient (TSEEY), and the total secondary electron emission coefficient exceeds 1 in a wide energy region in which electrons collide with the spacers 40. The total secondary electron emission coefficient (TSEEY) is represented by a total of a secondary electron emission coefficient (SEEC) and a backscattered electron coefficient (BC). As shown in FIG. 21, the total secondary electron emission coefficient is a function of electron beam energy and is maximized near 450 eV in almost all substances. Also, the total secondary electron emission coefficient changes with the angle θ of incidence on a surface of a material. FIG. 21 shows a relation between the electron beam energy and the total secondary electron emission coefficient (TSEEY) at each of the incidence angles θ of 0°, 30°, 60°, and 80°. FIG. 21 also indicates that when electrons are incident obliquely on the spacers 40, the total secondary electron emission coefficient is increased.
FIG. 22A shows an energy distribution of electrons colliding with the spacers 40, and FIG. 22B shows an angle distribution of electrons colliding with the spacers 40. When electron beams with an energy of 10 keV are applied to the fluorescent layers 22, backscattered electrons or the like move toward the cathode panel side. However, since the electric field on the anode panel side is positive, so-called parabolic orbits are created. Therefore, the electrons are incident (collide) on the spaces 40 with various energies (refer to FIG. 22A) and at various angles (refer to FIG. 22B). Ideally, when the total secondary electron emission coefficient of the side surfaces of the spacers 40 is 1, charge-up does not occur in the side surfaces of the spacers 40. However, it may be impossible to control the total secondary electron emission coefficient to 1 for electrons incident (colliding) on the spacers 40 at various angles and with various energies.
As a result, a positive charge occurs in the side surfaces of the spacer 40, and parallel electric fields near the spacers 40 are bent, thereby bending electron beam orbits. Furthermore, bending the electron beam orbits causes further collision of electrons with the spacers 40, and charge-up in the spacers 40 is further increased, thereby further bending the electron beam orbits (refer to FIG. 20). In this state, electron beams do not collide with the desired fluorescent layers 22 due to the disturbance of the electron beam orbits near the spacers 40 and thus the formed image is distorted near the spacers 40. As a result, the formation of an image is significantly affected, and the spacers 40 become visible. In addition, in some cases, the components of a display may be damaged by creeping discharge due to the positive charge. Furthermore, degradation in the antistatic film formed on the side surfaces of the spacers 40 changes with time due to the positive charge, and the antistatic films are decreased in resistance, thereby causing the problem of distorting the electric fields and bending the electron beam orbits. Therefore, it is a very important technical matter to rapidly remove the electric charge from the side surfaces of the spacers 40.
A technique for rapidly removing the electric charge from the sides of spacers is disclosed in, for example, U.S. Pat. No. 3,099,003. In the technique disclosed in this patent publication, a spacer includes an insulating base and a two-layer film including first and second layers formed on the side surface of the insulating base. It is also disclosed that the electric charge accumulated in the spacer is rapidly removed through the first layer.
In order to rapidly remove the electric charge from the side surface of a spacer, for example, U.S. Pat. No. 3,466,981 discloses a technique of forming a low-resistance film on each of portions of a spacer which contact an anode panel component and a cathode panel component, respectively.